In this position, you will be a part of the Centralized Design Automation Operations team (CDAO) working on the development and support of next generation IC design flows for analog, digital and/or full custom circuits. As an experienced CAD engineer in the team, you will be required to assume a technical leadership role in the development of these design flows for multiple engineering customers (Internal or External) using industry standard EDA software such as Cadence, Mentor, Synopsys, etc.... You may be responsible for tool evaluation, selection, support, collateral (PDK, FDK) or flow development for the Non-Volatile Memory Group (NVM, NSG) or other Intel Engineering groups under TMG, DCSG, IAG, MCG or Intel Labs. Qualifications
You must possess a minimum of a Bachelor of Science degree in Electrical Engineering or Computer Engineering with at least 5 years of experience in IC Design or Computer Aided Design (CAD) or a Masters Degree in Electrical Engineering or Computer Engineering with at least 2 years of related experience.
Additional qualifications include:
- Demonstrate experience with various Electronic Design Automation (EDA) tools, flows, and architecture.
- Demonstrate a solid understanding of Integrated Circuit (IC) simulation tools (e.g. HSPICE, HSIM, etc.) and related methodologies.
- Demonstrate experience in front-to-back IC design flows with a focus on analog and mixed signal (AMS) solutions.
- Demonstrate experience in building and qualifying parasitic extraction flows and associated technology files.
- Demonstrate experience with the Cadence Virtuoso
environment, including Schematic Composer and Layout Editor.
- Demonstrate experience with multiple CAD flows: custom frontend and backend, parasitic extraction, PDK development.
- Industry experience with Cadence, Synopsys and/or Mentor tools would be a plus.
- Demonstrate knowledge of Complementary Metal-Oxide Semiconductor (CMOS) processing, Very Large Scale Integration design (VLSI) and device physics.
- Experience in Linux and data-management software (e.g. Clearcase, DesignSync, SVN) is expected.
- Demonstrate experience to interface with engineers and managers by providing schedule updates and roadmap plans.
- Demonstrate experience in C++, shell, Perl, Tcl/Tk, SKILL, or Python programming.
- Demonstrate experience to lead small groups of junior engineers and working cross-site is expected for this role.
- A Master of Science (MS) degree in Electrical Engineering and/or Computer Engineering and/or Computer Science would be an added advantage
- Demonstrate experience in RF tools and flows (or process modeling).
- Prior experience with Intel NOR-Flash DA Flows and Environments (Custom-CAD flows).
- Familiarity with Analog frontend or Logic design flows (APR, Verilog, RTL, Synthesis, SPICE simulation).
- Familiarity with Physical design and verification flows (DRC, LVS, Parasitic extraction)
- Familiarity with data management (DesignSync, Subversion or other).
- Team player and self-motivated technical leader.
For additional questions about this position, please contact the hiring manager firstname.lastname@example.org.